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  1. 1 point
    johnnytai4

    Problem on AR5B95 on Yosemite

    OMG It's work!! thank you so much!!
  2. 1 point
    Mirone

    Problem on AR5B95 on Yosemite

    try this kext:IO80211Family.kext.zip
  3. 1 point
    Knoddix_12

    Kext for Intel GMA 3100

    Hi one and all I have searched hi and low for a kext for the intel GMA 3100 graphics chip and have not found a single kext for it I keep getting results for the GMA X3100 which does not help my machine is running 10.9.4 and everything seems to be running fine except the graphics acceleration portion which prevents me playing video files among other things I'm thinking if I can't find a kext for it I might have to get another graphics card one that is low profile so if anyone knows where the GMA 3100 kext is hiding or if anyone can recommend a compatible low profile graphics card the help would be greatly appreciated
  4. 1 point
    Let's continue with P-States. The relevant objects in the SSDT for P-States are _PCT, _PSS and _PPC. _PCT stands for Performance Control (ACPI spec chapter 8.4.4.1)and declares an interface that allows OSPM to transition to a specific performance state. I know to methods: one uses directly the CPU Performance Control Register (FFixedHW, 0x199) and the other one uses SystemIO to configure the P-State. I tried both methods on my system. Both are able to change the frequency, but only the direct method using the PERF_CTRL register could also change the voltage (checked with CPU-I). _PSS stands for Performance Supported States(ACPI spec chapter 8.4.4.2). It declares the supported performance states to OSPM. It returns a package of all available P-States and each one declares Core Frequency, Power, Latency, Bus Master Latency, Control and Status. _PPC stands for Performance Present Capabilities (ACPI spec chapter 8.4.4.3). It's is a method that dynamically indicates to OSPM the number of performance states currently supported. Returning 0 is fine and indicates that all P-States listed in _PSS are available. My system looks like this: DefinitionBlock ("ssdt_cpu0ist.aml", "SSDT", 1, "PmRef", "Cpu0Ist", 0x00003000) { External (CFGD) External (\_PR_.CPU0, DeviceObj) Scope (\_PR.CPU0) { Method ([COLOR=Red]_PPC[/COLOR], 0, NotSerialized) { Return (0x00) } Method ([COLOR=Blue]_PCT[/COLOR], 0, NotSerialized) { If (LEqual (And (CFGD, 0x00060000), 0x00020000)) { Return (Package (0x02) { ResourceTemplate () { Register (SystemIO, 0x10, 0x00, 0x0000000000000880, ,) }, ResourceTemplate () { Register (SystemIO, 0x10, 0x00, 0x0000000000000882, ,) } }) } If (LEqual (And (CFGD, 0x00060000), 0x00040000)) { Return (Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) } }) } If (LOr (And (CFGD, 0x4000), And (CFGD, 0x00010000))) { Return (Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) } }) } Return (Package (0x02) { ResourceTemplate () { Register (SystemIO, 0x10, 0x00, 0x0000000000000880, ,) }, ResourceTemplate () { Register (SystemIO, 0x10, 0x00, 0x0000000000000882, ,) } }) } Method ([COLOR=Green]_PSS[/COLOR], 0, NotSerialized) { If (LEqual (And (CFGD, 0x00060000), 0x00020000)) { Return (SPSS) } If (LEqual (And (CFGD, 0x00060000), 0x00040000)) { Return (NPSS) } If (LOr (And (CFGD, 0x4000), And (CFGD, 0x00010000))) { Return (NPSS) } Return (SPSS) } Name (SPSS, Package (0x02) { Package (0x06) { 0x00000B12, 0x000157C0, 0x000000A0, 0x0000000A, 0x00000036, 0x00000000 }, Package (0x06) { 0x000007D0, 0x0000DAC0, 0x000000A0, 0x0000000A, 0x00000136, 0x00000001 } }) Name (NPSS, Package (0x02) { Package (0x06) { 0x00000B12, 0x000157C0, 0x0000000A, 0x0000000A, 0x00004825, 0x00004825 }, Package (0x06) { 0x000007D0, 0x0000DAC0, 0x0000000A, 0x0000000A, 0x00000616, 0x00000616 } }) } }The CFGD is declared external here and it's defined in the "Root" SSDT: Name (CFGD, 0x040383F2)Until today I was not able to find a BIOS setting which changes CFGD in a way which has influence on the P-States. How they resolve: LEqual (And (0x040383F2, 0x00060000), 0x00020000) = TRUE LEqual (And (0x040383F2, 0x00060000), 0x00040000) = FALSE LOr (And (0x040383F2, 0x00004000), And (0x040383F2, 0x00010000)) = TRUE This means in my case that the P-States a handled using SystemIO, which in turn only switches the frequency and no the voltage. It coud be fixed by modifying CFGD to: Name (CFGD, 0x040583F2)Or just by removing all the SystemIO stuff which could look like this: DefinitionBlock ("ssdt_cpu0ist.aml", "SSDT", 1, "PmRef", "Cpu0Ist", 0x00003000) { External (CFGD) External (\_PR_.CPU0, DeviceObj) Scope (\_PR.CPU0) { Method (_PPC, 0, NotSerialized) { Return (0x00) } Method (_PCT, 0, NotSerialized) { Return (Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) } }) } Method (_PSS, 0, NotSerialized) { Return (NPSS) } Name (NPSS, Package (0x02) { Package (0x06) { 0x00000B12, 0x000157C0, 0x0000000A, 0x0000000A, 0x00004825, 0x00004825 }, Package (0x06) { 0x000007D0, 0x0000DAC0, 0x0000000A, 0x0000000A, 0x00000616, 0x00000616 } }) } }To be continued... Please do not post until I'm finished!
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