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dantoine

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About dantoine

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  • Birthday 03/12/1980
  1. Hi, i have found this code for E6550-Speedstep. Scope (_PR) { Processor (CPU0, 0x00, 0x00000410, 0x06) {} Processor (CPU1, 0x01, 0x00000410, 0x06) {} Processor (CPU2, 0x02, 0x00000410, 0x06) {} Processor (CPU3, 0x03, 0x00000410, 0x06) {} } Scope (_PR.CPU0) { Method (_PSS, 0, NotSerialized) { Return (Package (0x03) { Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x072A, Zero }, Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x0623, One }, Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x0616, 0x02 } }) } Method (_PSD, 0, NotSerialized) { Return (Package (0x05) { 0x05, Zero, Zero, 0xFC, 0x04 }) } Method (_CST, 0, NotSerialized) { Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, 0x9D, 0x03E8 } }) } } Scope (_PR.CPU1) { Method (_PSS, 0, NotSerialized) { Return (^^CPU0._PSS ()) } Method (_PSD, 0, NotSerialized) { Return (^^CPU0._PSD ()) } Method (_CST, 0, NotSerialized) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, One, Zero, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, One, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000415, // Address ,) }, 0x03, 0x55, 0xFA } }) } } Scope (_PR.CPU2) { Method (_PSS, 0, NotSerialized) { Return (^^CPU0._PSS ()) } Method (_PSD, 0, NotSerialized) { Return (^^CPU0._PSD ()) } Method (_CST, 0, NotSerialized) { Return (^^CPU1._CST ()) } } Scope (_PR.CPU3) { Method (_PSS, 0, NotSerialized) { Return (^^CPU0._PSS ()) } Method (_PSD, 0, NotSerialized) { Return (^^CPU0._PSD ()) } Method (_CST, 0, NotSerialized) { Return (^^CPU1._CST ()) } } But i am wondering why there are exist 4 cpu entries (cpu0 to cpu4)? Because the e6550 is a duo processor. Must i now delete cpu2 and cpu3 entries? For example so?: Scope (_PR) { Processor (CPU0, 0x00, 0x00000410, 0x06) {} Processor (CPU1, 0x01, 0x00000410, 0x06) {} } Scope (_PR.CPU0) { Method (_PSS, 0, NotSerialized) { Return (Package (0x03) { Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x072A, Zero }, Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x0623, One }, Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x0616, 0x02 } }) } Method (_PSD, 0, NotSerialized) { Return (Package (0x05) { 0x05, Zero, Zero, 0xFC, 0x04 }) } Method (_CST, 0, NotSerialized) { Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, 0x9D, 0x03E8 } }) } } Scope (_PR.CPU1) { Method (_PSS, 0, NotSerialized) { Return (^^CPU0._PSS ()) } Method (_PSD, 0, NotSerialized) { Return (^^CPU0._PSD ()) } Method (_CST, 0, NotSerialized) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, One, Zero, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, One, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000415, // Address ,) }, 0x03, 0x55, 0xFA } }) } }
  2. Hi, have someone experiences with speedstep for a E6550? What i must insert into the DSDT File?
  3. Can please someone post the speedstep-dsdt-code for a E6550 processor?
  4. Hi richiem, I use fakesmc.kext, LegacyHDA.kext and OpenHaltRestart.kext. I have vanilla SpeedStep in my DSDT.
  5. Hi, I have problems to use USB-Harddrives in 10.6.2 with 64bit Kernel. With the 32bit Kernel I can use the drives. But with 64bit I can't activate the drives. Can someone give tips how to use also with 64bit Kernel?
  6. Hi kantok, can you please tell me how do that?
  7. Can someone show a working com.apple.boot.plist?
  8. I have a EP45-DS3. USB-Stick with Chameleon working perfect. I use the following code. <key>EthernetBuiltIn</key> <string>y</string> <key>GraphicsEnabler</key> <string>y</string> But with pc efi 10.3 the GraphicsEnabler don't work. My Geforce 8800 GT is not detected. Do you some tipps?
  9. Hi, i have a PCI Asus WL-138g V2 as Wifi-Card. With the EFI-X Modul it worked perfect. But if I use Chameleon, the Wifi-Speed is very slow (10kB/s). Is it possible to make an DSDT-Patch for the card? Or need I extra kext-files to work?
  10. Hi AsereBLN, I have used your new DSDT for EP45-DS3. After the start from chameleon I can see that the graphic-card is detected correct. But in 10.5.8 my graphic-card (Asus Geforce 8800GT 512 MB) is not detected and the sleep-mode also don't work. I have also used the same kexts as you. But nothing helps. My Bios-Version is F9.
  11. Hi, I also have the automatic sleep problem in Leopard. Sometimes it works and sometimes not. But now I use the small tool "Please Sleep". It puts the Computer into sleep, when the system is sending the sleep-trigger. And it works great.
  12. dantoine

    DSDT patch requests

    Hi Mike, here is my IOReg-Dump.
  13. Hi, I have a EP45-DS3 v1 (F9). I would like to know what kext it necessary for 10.5 and 10.6?
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