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mm67

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About mm67

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  • Birthday 08/01/1967
  1. Yes, new version just does that automatically, new feature is more useful for those who haven't yet added speedstepping to dsdt.
  2. They don't need to be changed when you overclock. Gigabyte P45 boards seem to have a problem with C-states and Vcore setting. At least my -UD3 and -UD3LR boards loose C-states if I use any other Vcore setting than normal. Same happens also on Windows.
  3. RC5 is not yet official but it works just fine. Best new feature is automatic P- and C-state generation, editing dsdt is no more needed for speedstepping.
  4. Take a look at ICH10 datasheet page 455. Bit 7 of that register tells if cpu has entered a C-state deeper than C2. Problem is that your bios sets bit 0 of that register which disables functionality of bit 7 so you can't check for C4 this way. I also have the same problem on my MSI board so I really can't tell for sure if C4 works when using OS X. I also have only C-state tech option on MSI, no selection of which C-states I want, but running Windows or Linux I can see that board uses C1, C2 and C4.
  5. I think those page numbers refer to Acpispec v.4 document, that's 727 pages of light reading After that you can continue with 840 pages of ICH10 datasheet ...
  6. Supported C-states for our CPU's can be found from these Intel datasheets: http://www.intel.com/design/processor/specupdt/318727.htm The CST package is just a copy from my MSI P43 board's SSDT dump. If you need a working CST package for X58 board then I would use MacPro4,1 SSDT dump as an example.
  7. That Q9650 does support deeper C-states so this is what CST should look like: Name (CST, Package (0x04) { // C States - returns a list of supported C-states. 8.4.2.1 p314 0x03, Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x000, 0x0,)},0x01,0x01,0x03E8} Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x010, 0x1,)},0x02,0x01,0x01F4} Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x030, 0x3,)},0x04,0x39,0x0064} }) //End CST
  8. This scope PR should work for Guidorusso: Scope (_PR) { Processor (CPU0, 0x00, 0x00000410, 0x06) { Alias (PSS, _PSS) Alias (CST, _CST) } Processor (CPU1, 0x01, 0x00000410, 0x06) { Alias (PSS, _PSS) Alias (CST, _CST) } Processor (CPU2, 0x02, 0x00000410, 0x06) { Alias (PSS, _PSS) Alias (CST, _CST) } Processor (CPU3, 0x03, 0x00000410, 0x06) { Alias (PSS, _PSS) Alias (CST, _CST) } Method (PSS, 0, NotSerialized) { Return (Package (0x06) { Package (0x06){Zero,Zero,0x0A,0x0A,0x4820,0x4820}, Package (0x06){Zero,Zero,0x0A,0x0A,0x081E,0x081E}, Package (0x06){Zero,Zero,0x0A,0x0A,0x471C,0x471C}, Package (0x06){Zero,Zero,0x0A,0x0A,0x071A,0x071A}, Package (0x06){Zero,Zero,0x0A,0x0A,0x4618,0x4618}, Package (0x06){Zero,Zero,0x0A,0x0A,0x0616,0x0616} }) } Method (CST, 0, NotSerialized) { Return (Package (0x04) { 0x3, Package (0x4){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x000,,)},One,One,0x3E8}, Package (0x4){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x010,,)},0x2,One,0x1F4}, Package (0x4){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x030,,)},0x4,0x96,0x64} }) } } But I think that he also needs to inject fake device-id to LPC, I think you have that code in your dsdt.
  9. Those values are correct: 6, 6.5, 7, 7.5, 8 and 8.5. Values starting with 48 are the .5 values. Exactly same as my FID and VID values.
  10. Maybe this helps ? http://www.efixusers.com/showpost.php?p=5604&postcount=9
  11. You should still get correct VID values for P-states, you are now using Knotty 's PSS table, your values may be bit different. But now you are really close
  12. Something like this should work: OperationRegion (SMME, SystemIO, 0x0830, One) Field (SMME, ByteAcc, NoLock, Preserve) { , 4, SLPE, 1 } Name (WOTB, Zero) Name (WSSB, Zero) Name (WAXB, Zero) Method (_PTS, 1, NotSerialized) { Store (Arg0, DBG8) PTS (Arg0) Store (Zero, Index (WAKP, Zero)) Store (Zero, Index (WAKP, One)) If (LAnd (LEqual (Arg0, 0x04), LEqual (OSFL (), 0x02))) { Sleep (0x0BB8) } Store (ASSB, WSSB) Store (AOTB, WOTB) Store (AAXB, WAXB) Store (Arg0, ASSB) Store (OSFL (), AOTB) Store (OSYS (), OSTP) Store (Zero, AAXB) If (LEqual (Arg0, 0x05)) { Store (Zero, SLPE) Sleep (0x10) } }
  13. What that setting does is that native mode let's OS decide which irq's to use, disabled mode means that irq's are fixed. Both should work.
  14. New ones have even shutdown working out of the box ? On my MSI board I had to fix that, everything else pretty much works as is.
  15. It's impossible for anyone to answer that question unless they know your setup exactly, what we all need is fakesmc.kext. What else you need depends on your hardware and dsdt. I for example use only fakesmc on my MSI board, on my Gigabyte board I use fakesmc and IOAHCIBlockStorageInjector. I don't need nothing else because this new booter and shutdown fix in dsdt allow me to remove PlatformUUID and OpenHaltRestart. I don't use onboard audio, ethernet or JMicron controller so no kext files for those either. For my Wlan card I don't need AtherosFix.kext because I have patched a fake device-id into dsdt.
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