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dantoine

Speedstep for E6550

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Hi, i have found this code for E6550-Speedstep.

Scope (_PR)
{
Processor (CPU0, 0x00, 0x00000410, 0x06) {}
Processor (CPU1, 0x01, 0x00000410, 0x06) {}
Processor (CPU2, 0x02, 0x00000410, 0x06) {}
Processor (CPU3, 0x03, 0x00000410, 0x06) {}
}

Scope (_PR.CPU0)
{
Method (_PSS, 0, NotSerialized)
{
Return (Package (0x03)
{
Package (0x06)
{
Zero,
Zero,
0x0A,
0x0A,
0x072A,
Zero
},

Package (0x06)
{
Zero,
Zero,
0x0A,
0x0A,
0x0623,
One
},

Package (0x06)
{
Zero,
Zero,
0x0A,
0x0A,
0x0616,
0x02
}
})
}

Method (_PSD, 0, NotSerialized)
{
Return (Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x04
})
}

Method (_CST, 0, NotSerialized)
{
Return (Package (0x02)
{
One,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},

One,
0x9D,
0x03E8
}
})
}
}

Scope (_PR.CPU1)
{
Method (_PSS, 0, NotSerialized)
{
Return (^^CPU0._PSS ())
}

Method (_PSD, 0, NotSerialized)
{
Return (^^CPU0._PSD ())
}

Method (_CST, 0, NotSerialized)
{
Return (Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
,)
},

One,
Zero,
0x03E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
One,
0x01F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},

0x03,
0x55,
0xFA
}
})
}
}

Scope (_PR.CPU2)
{
Method (_PSS, 0, NotSerialized)
{
Return (^^CPU0._PSS ())
}

Method (_PSD, 0, NotSerialized)
{
Return (^^CPU0._PSD ())
}

Method (_CST, 0, NotSerialized)
{
Return (^^CPU1._CST ())
}
}

Scope (_PR.CPU3)
{
Method (_PSS, 0, NotSerialized)
{
Return (^^CPU0._PSS ())
}

Method (_PSD, 0, NotSerialized)
{
Return (^^CPU0._PSD ())
}

Method (_CST, 0, NotSerialized)
{
Return (^^CPU1._CST ())
}
}

But i am wondering why there are exist 4 cpu entries (cpu0 to cpu4)? Because the e6550 is a duo processor. Must i now delete cpu2 and cpu3 entries? For example so?:

Scope (_PR)
{
Processor (CPU0, 0x00, 0x00000410, 0x06) {}
Processor (CPU1, 0x01, 0x00000410, 0x06) {}
}

Scope (_PR.CPU0)
{
Method (_PSS, 0, NotSerialized)
{
Return (Package (0x03)
{
Package (0x06)
{
Zero,
Zero,
0x0A,
0x0A,
0x072A,
Zero
},

Package (0x06)
{
Zero,
Zero,
0x0A,
0x0A,
0x0623,
One
},

Package (0x06)
{
Zero,
Zero,
0x0A,
0x0A,
0x0616,
0x02
}
})
}

Method (_PSD, 0, NotSerialized)
{
Return (Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x04
})
}

Method (_CST, 0, NotSerialized)
{
Return (Package (0x02)
{
One,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},

One,
0x9D,
0x03E8
}
})
}
}

Scope (_PR.CPU1)
{
Method (_PSS, 0, NotSerialized)
{
Return (^^CPU0._PSS ())
}

Method (_PSD, 0, NotSerialized)
{
Return (^^CPU0._PSD ())
}

Method (_CST, 0, NotSerialized)
{
Return (Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
,)
},

One,
Zero,
0x03E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
One,
0x01F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},

0x03,
0x55,
0xFA
}
})
}
}

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